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NCP1588 Low Voltage Synchronous Buck Controller
The NCP1588 is a low cost PWM controller designed to operate from a 5 V or 12 V supply. This device is capable of producing an output voltage as low as 0.8 V. This device is capable of converting voltage from as low as 2.5 V. This 10-pin device provides an optimal level of integration to reduce size and cost of the power supply. The NCP1588 provides a 1.5 A gate driver design and an internally set 300 kHz oscillator. In addition to the 1.5 A gate drive capability, other efficiency enhancing features of the gate driver include adaptive non-overlap circuitry. The NCP1588 also incorporates an externally compensated error amplifier. Protection features include programmable short circuit protection and undervoltage lockout (UVLO).
Features http://onsemi.com MARKING DIAGRAM
DFN10 MT SUFFIX CASE 485C 1588 A L Y W G 1588 ALYWG G
* * * * * * * * * * * * * * * *
VCC Range from 4.5 to 13.2 V 300 kHz Internal Oscillator Boost Pin Operates to 26.4 V Voltage Mode PWM Control 0.8 V 1.0% Internal Reference Voltage Adjustable Output Voltage Internal 1.5 A Gate Drivers 80% Max Duty Cycle Input Under Voltage Lockout Programmable Current Limit This is a Pb-Free Device Graphics Cards Desktop Computers Servers / Networking DSP & FPGA Power Supply DC-DC Regulator Modules
= Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Device
(Note: Microdot may be in either location)
PIN CONNECTIONS
BOOT LX UG LG GND 1 2 3 4 5 (Top View) 10 9 8 7 6 PGOOD VOS FB COMP/EN VCC
Applications
ORDERING INFORMATION
Device NCP1588MTR2G Package DFN10 (Pb-Free) Shipping 3000/Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2007
1
June, 2007 - Rev. 0
Publication Order Number: NCP1588/D
NCP1588
VCC = 4.5 V - 13.2 V VBST = 4.5 V - 15 V VIN = 2.5 V - 13.2 V 3x22mF
1500mF
1mF
1500mF
2x0.22mF
VCC 0.1mF COMP/EN C1 0.0015mF R2 17.08kW C2 0.007mF FB GND R4 3.878kW R1 4.12kW C3 0.014mF 1.02k R3 74.2W R9 R10 1.02k UG NTD4809 PGOOD BOOT
LX NTD4806 LG VOS ROCSET 2.2
1mH
VOUT 1.65 V
2x1800mF 4.7nF
GND
Figure 1. Typical Application Diagram
PGOOD
10
VOS 9
PGOOD MONITOR OV and UV 0.8 V (VREF)
10% of Vref 25% of Vref POR UVLO 6 VCC
FAULT
LATCH
+ FAULT
VOCP
FB
8
+ 0.8 V (VREF)
1
+ -
BOOT UG
R PWM OUT Q 3
S
2 + CLOCK RAMP 7 OSC SOFT START 2V + VCC 4
LX
COMP/EN
LG
OSC
FAULT
5
GND
Figure 2. Detailed Block Diagram
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NCP1588
PIN FUNCTION DESCRIPTION
Pin No. 1 Symbol BOOT Description Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to BOOT pin). Connect a capacitor (CBOOT) between this pin and the LX pin. Typical values for CBOOT range from 0.1 mF to 1 mF. Ensure that CBOOT is placed near the IC. Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top MOSFET. Top gate MOSFET driver pin. Connect this pin to the gate of the top N-channel MOSFET. Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N-channel MOSFET. IC ground reference. All control circuits are referenced to this pin. Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 mF capacitor to GND. Ensure that this decoupling capacitor is placed near the IC. Compensation Pin. This is the output of the error amplifier (EA) and the non-inverting input of the PWM comparator. Use this pin in conjunction with the FB pin to compensate the voltage-control feedback loop. Pull this pin low for disable. This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to com pensate the voltage-control feedback loop. Connect this pin to the output resistor divider (if used) or directly to Vout. Offset voltage pin from Vout. Power Good output. Open drain type output that is flagged low if 10% of Vout.
2 3 4 5 6 7
LX UG LG GND VCC COMP/EN
8
FB
9 10
VOS PGOOD
ABSOLUTE MAXIMUM RATINGS
Pin Name Main Supply Voltage Input Bootstrap Supply Voltage Input Symbol VCC BOOT VMAX 15 V 30 V wrt/GND 38-40 V < 100 ns 15 V wrt/LX 25 V 30 V for < 100 ns 30 V wrt/GND 15 V wrt/LX 40 V for < 100 ns VCC + 0.3 V 3.6 V 3.6 V 7V VMIN -0.3 V -0.3 V
Switching Node (Bootstrap Supply Return) High-Side Driver Output (Top Gate)
LX UG
-5 V -0.3 V wrt/LX
Low-Side Driver Output (Bottom Gate) Feedback, VOS COMP/EN PGOOD
LG FB, VOS COMP/EN PGOOD
-0.3 V -2 V < 100 ns -0.3 V -0.3 V -0.3 V
MAXIMUM RATINGS
Rating Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case NCP1588 Operating Junction Temperature Range NCP1588 Operating Ambient Temperature Range Storage Temperature Range Moisture Sensitivity Level Symbol RqJA RqJC TJ TA Tstg MSL Value 165 45 0 to 150 0 to 70 -55 to +150 1 Unit C/W C/W C C C 260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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NCP1588
ELECTRICAL CHARACTERISTICS (0C < TA < 70C, 0C < TJ < 125C (NCP1588); 4.5 V < VCC < 13.2 V, 4.5 V < BOOT < 26.4 V, CUG = CLG = 1.0 nF (REF:NTD30N02), for min/max values unless otherwise noted.)
Characteristic Input Voltage Range Boost Voltage Range 13.2 V wrt LX Conditions Min 4.5 4.5 Typ Max 13.2 26.4 Unit V V
Supply Current
Quiescent Supply Current Boost Quiescent Current VFB = 1.0 V, No Switching, VCC = 13.2 V VFB = 1.0 V, No Switching 1.0 140 1.75 mA mA
Undervoltage Lockout
UVLO threshold UVLO hysteresis VCC Rising Edge 3.8 0.37 4.0 V V
Switching Regulator
VFB Feedback Voltage, control loop in regulation Oscillator Frequency Ramp-Amplitude Voltage Minimum Duty Cycle Maximum Duty Cycle LG minimum on time 70 TA = 0 to 70C TA = 0 to 70C 0.792 270 0.8 300 1.1 0 75 500 80 0.808 330 V KHz V % % ns
Error Amplifier
Open loop dc gain Output source current Output sink current Input Offset Voltage Input Bias Current Unity Gain Bandwidth Disable Threshold Output Sink current during disable 15 0.3 0.5 100 Vfb < 0.8 V Vfb > 0.8 V 70 2.0 2.0 -2.0 0 0.1 2.0 1.0 80 DB mA mV mA Mhz V mA
Gate Drivers
Upper Gate source Upper Gate sink Lower Gate source Lower Gate sink UG falling to LG rising delay LG falling to UG rising delay VCC = 12 V VCC = 12 V, UG-LX < 2.0 V, LG > 2.0 V VCC = 12 V, LG < 2.0 V, UG > 2.0 V 1.5 1.0 30 30 90 60 VCC = 5 V, VUG - VLX = 2.5 V 1.5 1.4 A W A W ns ns
Soft-Start
Soft-Start time 3.0 7.0 ms
Power Good
Output Saturation Voltage OVP threshold to part disable UVP threshold to part disable OVP threshold to PGOOD output low UVP threshold to PGOOD output low IPG = 4 mA, VCC = 12 Vdc 1.0 0.6 0.88 0.72 0.4 V V V V V
Overcurrent Protection
OC Current source Sourced from LG pin, before SS 10 mA
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NCP1588
TYPICAL CHARACTERISTICS
305 VCC = 12 V VREF, REFERENCE (mV) 80 fSW, FREQUENCY (kHz) 303 VCC = 5.0 V 808 806 804 802 800 798 796 794 295 0 20 40 60 TJ, JUNCTION TEMPERATURE (C) 792 0 20 40 60 80
301
299
297
TJ, JUNCTION TEMPERATURE (C)
Figure 3. Oscillator Frequency (fSW) vs. Temperature
4.0 3.5 3.0 ICC (mA) 2.5 2.0 1.5 1.0 0 -556 -558 OCP THRESHOLD (mV) -560 -562 -564 -566 -568 -570 20 40 60 80 0
Figure 4. Reference Voltage (VREF) vs. Temperature
20
40
60
80
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 5. ICC vs. Temperature
Figure 6. OCP Threshold with 55k Rset vs. Temperature
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NCP1588
APPLICATIONS INFORMATION
Overcurrent Protection (OCP) Internal Soft -Start
The low-side RDSon sense is implemented by comparing the voltage at the LX, at the end of LG on time to an internally generated fixed voltage. If the phase voltage is lower than OCP trip voltage, an overcurrent condition occurs and a counter is initiated. When the counter completes after two clock cycles, the PWM logic and both HS-FET and LS-FET are turned off. Power has to be recycled to exit out of the overcurrent fault. The minimum turn-on time of the LS-FET is set to be 500 ns. NCP1588 allows to easily program an Overcurrent Threshold ranging from 50 mV to 550 mV, simply by adding a resistor (ROCSET) between LG and GND. During a short period of time following VCC rising over UVLO threshold, an internal 10 mA current (IOCSET) is sourced from LG pin, determining a voltage drop across ROCSET. This voltage drop will be sampled and internally held by the device as OverCurrent Threshold. The OC setting procedure overall time length is about 4.2 ms. Connecting a ROCSET resistor between LG and GND, the programmed threshold will be:
I OCth + I OCSET @ R OCSET R DS(on)
The NCP1588 features an internal soft-start function, which reduces the inrush current and overshoot of the output voltage. Figure 7. shows a typical soft-start sequence. Soft-Start is achieved by ramping the internal reference using the oscillator clock (64 steps from 0 V to 0.8 V of VREF). The order of startup sequence is as follows: UVLO OCP programming Comp voltage reach the lower end of the Ramp voltage (1.1 V). The typical soft-start time is 4.2 ms. The internal soft-start is held low when the part is in UVLO or Disable mode.
Power Good
Power Good is an open drain and active high output. This output can be pulled up high to the appropriate level with an external resistor. It monitors the output voltage through the VOS pin. The PGOOD is flagged low for 10% of Vout for OV/UV trip points respectively. The separate VOS input is not slowed down by the compensation on the VFB pin. The PGOOD output can deliver a max of 4 mA sink current at 0.4 V when de-asserted. The PGOOD pin is held low during soft-start. Once soft-start is complete PGOOD goes high if there are no faults without any delays associated to it.
Undervoltage Protection
RSET values range from 5 kW to 55 kW. In case ROCSET is not connected, the device switches the OCP threshold to a fixed 640 mV value: an internal safety clamp on BG is triggered as soon as LG voltage reaches 700 mV, enabling the 640 mV fixed threshold and ending OC setting phase. The current trip threshold tolerance is 25 mV. The accuracy of the set point is best at the highest set point. The accuracy will decrease as the set point decreases.
If the voltage at VOS pin drops below UV threshold, the device turns off both HS and LS MOSFETs, latching the condition. This requires a POR to recover.
Overvoltage Protection
If the voltage at VOS pin rises over OV threshold (1V typ), overvoltage protection turns off UG MOSFET and turns on LG MOSFET. The LG MOSFET will be turned off as soon as VOS goes below Vref/2 (0.4 V). The condition is latched, and requires POR to recover. The device still controls the LG MOSFET and can switch it on whenever VOS rises above 0.4 V.
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NCP1588
4.0 V 3.6 V
VCC
UVLO Fault
1.1 V COMP -0.7 V 700 mV
UG
50 mV OCP Program mable
LG
VOUT 0.8 V
Vfb UV Monitor POR UVLO SS NORMAL
Figure 7. Typical Startup Sequence
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NCP1588
0.88V 1.0V 0.88V 0.8V 0.72V 0.4V
VOS
0.8V 0.6V
PG
UG LG
Overvoltage
Undervoltage
Figure 8. Typical Power Good Function Feedback and Compensation Design Example: Voltage Mode Control Loop with TYPE III Compensation Converter Parameters:
The NCP1588 allows the output voltage to be adjusted from 0.8 V to 5.0 V via an external resistor divider network. The controller will try to maintain 0.8 V at feedback pin. Thus, if a resistor divider circuit was placed across the feedback pin to VOUT, the controller will regulate the output voltage proportional to the resistor divider network in order to maintain 0.8 V at the FB pin. The same formula applies to the VOS pin and the controller will maintain 0.8 V at the VOS pin.
VOUT
Input Voltage: VIN = 5 V Output Voltage: VOUT = 1.65 V Switching Frequency: 300 kHz Total Output Capacitance: COUT = 3600 mF Total ESR: ESR = 6 mW Output Inductance: LOUT: 1 mH Ramp Amplitude: VRAMP = 1 V
C1
R1 FB R4 R3 C3 R2
C2
Figure 9.
VOUT
R1 E/A + R4 VREF VCOMP
The relationship between the resistor divider network above and the output voltage is shown in the following equation:
R4 + R1 VREF VOUT * VREF
Figure 10.
The same formula can be applied to the feedback resistors at VOS.
R9 + R10 VREF VOUT * VREF
a.. Set a target for the close loop bandwidth at 1/6th of the switching frequency.
F cross_over :+ 50 kHz
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NCP1588
b.. Output Filter Double Pole Frequency
F lc :+ 1 2@p@ L OUT @ C OUT
Step 5: Place 2nd zero at the output filter double pole frequency.
R3 :+ R1
F
SW lc
F lc + 2.653 kHz
2@F
*1
c.. ESR Zero Frequency:
F ESR :+ 1 2 @ p @ C OUT @ C ESR
R3 + 74.169 W
Step 6: Place 2nd pole at half the switching frequency.
C3 :+ 1 p @ R3 @ F SW
F ESR + 7.368 kHz
C3 + 0.014 mF
Step 1: Set a value for R1 between 2 kW and 5 kW
R1 :+ 4.12 kW
Step 7: R4 is sized to maintain the feedback voltage to VREF = 0.8 V.
R4 :+ V REF @ R1 V OUT * V REF
Step 2: Pick compensation DC gain (R2/R1) for desired close loop bandwidth.
V RAMP :+ 1.1 V R2 :+ R1 @ V RAMP V IN @ F cross_over F lc
R4 + 3.878 kW The Component values for Type III Compensation are:
R2 + 17.085 kW
Step 3: Place 1st zero at half the output filter double pole frequency.
C2 :+ 2 @ L OUT @ C OUT R2 10 - 3 mF
C2 + 7.024
Step 4: Place 1st pole at ESR zero frequency.
C1 :+ C2 C2 @ R2 @ 2 @ p @ F ESR * 1 10 - 3 mF
R1 = 4.12 kW R2 = 17.085 kW R3 = 74.169 W R4 = 3.878 kW C1 = 0.0015 mF C2 = 0.007 mF C3 = 0.014 mF NOTE: Recommend to change values to industry standard component values.
C1 + 1.542
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NCP1588
PACKAGE DIMENSIONS
DFN10, 3x3, 0.5P CASE 485C-01 ISSUE A
D A B
EDGE OF PACKAGE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS ONTO BOTTOM SURFACE OF TERMINAL b. 6. DETAILS A AND B SHOW OPTIONAL VIEWS FOR END OF TERMINAL LEAD AT EDGE OF PACKAGE. DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 2.45 2.55 3.00 BSC 1.75 1.85 0.50 BSC 0.19 TYP 0.35 0.45 0.00 0.03
L1 E DETAIL A Bottom View (Optional)
EXPOSED Cu MOLD CMPD PIN 1 REFERENCE 2X 2X
0.15 C
DETAIL B
(A3) A A1
SEATING PLANE
0.10 C
10X
0.08 C SIDE VIEW A1 C
DETAIL B Side View (Optional)
D2
10X
DETAIL A 5
L
1
e
E2
10X
K
10 10X
6
b BOTTOM VIEW
2.1746
0.10 C A B 0.05 C
NOTE 3
10X
0.5651
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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EE EE EE
10X
0.15 C
CCC CCC CCC
TOP VIEW
A3
SOLDERING FOOTPRINT*
2.6016
1.8508
3.3048
0.3008
0.5000 PITCH
DIMENSIONS: MILLIMETERS
NCP1588/D

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